On-chip debugger solution with Trace for Freescale MPC55xx

The Freescale MPC55xx microcontroller family built on Power Architecture technology, comprises 32-bit microcontroller devices designed for engine management, advanced driver assistance, central body, and gateway applications. The Freescale MPC55xx microcontroller family is based on e200z1 core, which features a memory management unit (MMU) and the full 32-bit Power ISA instruction set as well as the ability to implement variable length encoding (VLE) instructions. A small footprint e200z0 core is added to the MPC5510 devices, which is designed to run the variable length encoding (VLE) instructions only, which delivers a high level of code density, significantly reducing memory requirements. According to the Nexus standard, MPC5500 family contains multiple Nexus clients that communicate over a single IEEEE-ISTO 5001-2003 Nexus Class 3 (or 2+) combined JTAG IEEEE 1149.1 auxiliary out interface. Combined, all of the Nexus clients are referred to as the Nexus development interface (NDI). Class 3 Nexus allows for program, data and ownership trace of the microcontroller execution without access to the external data and address buses. Class 2+ Nexus has no data trace comparing to the Class 3 Nexus. Communication to the NDI is handled via the auxiliary port and the JTAG port. Debug JTAG clock frequency must not exceed half CPU system clock frequency. iSYSTEM tools may be used as a debug system only or as a complex trace system.

 

On-Chip Debugger with advanced trace tool setup: iC3000 base unit + iTRACE PRO for Freescale MPC55xx